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00008 #include <lestes/backend_v2/structs/func_data.g.hh>
00009 #include <lestes/backend_v2/intercode/ge.g.hh>
00010 #include <lestes/backend_v2/intercode/pi_mem_factory.g.hh>
00011 #include <lestes/backend_v2/workers/alloc_int_finder.g.hh>
00012 #include <lestes/backend_v2/workers/bb_finder.g.hh>
00013 #include <lestes/md/registers/tm_register.g.hh>
00014 #include <lestes/md/registers/move_generator.g.hh>
00015 #include <lestes/md/types/tm_data_type_base.g.hh>
00016
00017 #include <lestes/std/list.hh>
00018 #include <lestes/std/pair.hh>
00019 #include <lestes/std/reflect.hh>
00020
00021 #include <lestes/backend_v2/workers/spillgen.g.hh>
00022
00023 package(lestes);
00024 package(backend_v2);
00025 package(workers);
00026
00027
00028
00029
00030
00031
00032
00033
00034 ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::workers::alloc_interval > > > spillgen::active_intervals_get() const
00035 {
00036 return active_intervals;
00037 }
00038
00039
00040
00041
00042
00043 void spillgen::active_intervals_set(const ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::workers::alloc_interval > > > & x)
00044 {
00045 spillgen::active_intervals = x;
00046 }
00047
00048
00049
00050
00051
00052 ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::workers::alloc_interval > > > spillgen::expired_intervals_get() const
00053 {
00054 return expired_intervals;
00055 }
00056
00057
00058
00059
00060
00061 void spillgen::expired_intervals_set(const ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::workers::alloc_interval > > > & x)
00062 {
00063 spillgen::expired_intervals = x;
00064 }
00065
00066
00067
00068
00069
00070 ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::workers::alloc_interval > > > spillgen::waiting_intervals_get() const
00071 {
00072 return waiting_intervals;
00073 }
00074
00075
00076
00077
00078
00079 void spillgen::waiting_intervals_set(const ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::workers::alloc_interval > > > & x)
00080 {
00081 spillgen::waiting_intervals = x;
00082 }
00083
00084
00085
00086
00087
00088 ptr< ::lestes::std::set< ulint > > spillgen::free_registers_get() const
00089 {
00090 return free_registers;
00091 }
00092
00093
00094
00095
00096
00097 void spillgen::free_registers_set(const ptr< ::lestes::std::set< ulint > > & x)
00098 {
00099 spillgen::free_registers = x;
00100 }
00101
00102
00103
00104
00105
00106 ptr< ::lestes::std::set< ulint > > spillgen::used_registers_get() const
00107 {
00108 return used_registers;
00109 }
00110
00111
00112
00113
00114
00115 void spillgen::used_registers_set(const ptr< ::lestes::std::set< ulint > > & x)
00116 {
00117 spillgen::used_registers = x;
00118 }
00119
00120
00121
00122
00123
00124 ptr< ::lestes::std::set< ulint > > spillgen::all_registers_get() const
00125 {
00126 return all_registers;
00127 }
00128
00129
00130
00131
00132
00133 void spillgen::all_registers_set(const ptr< ::lestes::std::set< ulint > > & x)
00134 {
00135 spillgen::all_registers = x;
00136 }
00137
00138
00139
00140
00141
00142 ptr< ::lestes::std::map< ulint, srp< ::lestes::backend_v2::workers::alloc_interval > > > spillgen::register_owners_get() const
00143 {
00144 return register_owners;
00145 }
00146
00147
00148
00149
00150
00151 void spillgen::register_owners_set(const ptr< ::lestes::std::map< ulint, srp< ::lestes::backend_v2::workers::alloc_interval > > > & x)
00152 {
00153 spillgen::register_owners = x;
00154 }
00155
00156
00157
00158
00159
00160 ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::pi_mem_factory > > > spillgen::free_spill_spaces_get() const
00161 {
00162 return free_spill_spaces;
00163 }
00164
00165
00166
00167
00168
00169 void spillgen::free_spill_spaces_set(const ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::pi_mem_factory > > > & x)
00170 {
00171 spillgen::free_spill_spaces = x;
00172 }
00173
00174
00175
00176
00177
00178 ptr< ::lestes::md::registers::move_generator > spillgen::move_gen_get() const
00179 {
00180 return move_gen;
00181 }
00182
00183
00184
00185
00186
00187 void spillgen::move_gen_set(const ptr< ::lestes::md::registers::move_generator > & x)
00188 {
00189 spillgen::move_gen = x;
00190 }
00191
00192
00193
00194
00195
00196 bool spillgen::registers_freed_get() const
00197 {
00198 return registers_freed;
00199 }
00200
00201
00202
00203
00204
00205 void spillgen::registers_freed_set(bool x)
00206 {
00207 spillgen::registers_freed = x;
00208 }
00209
00210
00211
00212
00213
00214 ptr< ::lestes::std::map< srp< ::lestes::backend_v2::intercode::pi_mem_factory >, srp< ::lestes::backend_v2::intercode::ge_pi > > > spillgen::spill_space_last_use_get() const
00215 {
00216 return spill_space_last_use;
00217 }
00218
00219
00220
00221
00222
00223 void spillgen::spill_space_last_use_set(const ptr< ::lestes::std::map< srp< ::lestes::backend_v2::intercode::pi_mem_factory >, srp< ::lestes::backend_v2::intercode::ge_pi > > > & x)
00224 {
00225 spillgen::spill_space_last_use = x;
00226 }
00227
00228
00229
00230
00231
00232 ptr< ::lestes::std::map< ulint, srp< ::lestes::backend_v2::intercode::ge_pi > > > spillgen::register_last_use_get() const
00233 {
00234 return register_last_use;
00235 }
00236
00237
00238
00239
00240
00241 void spillgen::register_last_use_set(const ptr< ::lestes::std::map< ulint, srp< ::lestes::backend_v2::intercode::ge_pi > > > & x)
00242 {
00243 spillgen::register_last_use = x;
00244 }
00245
00246
00247
00248
00249
00250 ptr< ::lestes::std::map< srp< ::lestes::backend_v2::intercode::ge_operand_reg >, srp< ::lestes::backend_v2::workers::alloc_interval > > > spillgen::op2interval_get() const
00251 {
00252 return op2interval;
00253 }
00254
00255
00256
00257
00258
00259 void spillgen::op2interval_set(const ptr< ::lestes::std::map< srp< ::lestes::backend_v2::intercode::ge_operand_reg >, srp< ::lestes::backend_v2::workers::alloc_interval > > > & x)
00260 {
00261 spillgen::op2interval = x;
00262 }
00263
00264
00265
00266
00267
00268 ptr< ::lestes::std::map< srp< ::lestes::backend_v2::intercode::ge_operand_reg >, srp< spillgen_group > > > spillgen::op2group_get() const
00269 {
00270 return op2group;
00271 }
00272
00273
00274
00275
00276
00277 void spillgen::op2group_set(const ptr< ::lestes::std::map< srp< ::lestes::backend_v2::intercode::ge_operand_reg >, srp< spillgen_group > > > & x)
00278 {
00279 spillgen::op2group = x;
00280 }
00281
00282
00283
00284
00285
00286 ptr< ::lestes::std::list< srp< spillgen_group > > > spillgen::groups_get() const
00287 {
00288 return groups;
00289 }
00290
00291
00292
00293
00294
00295 void spillgen::groups_set(const ptr< ::lestes::std::list< srp< spillgen_group > > > & x)
00296 {
00297 spillgen::groups = x;
00298 }
00299
00300
00301
00302
00303
00304 ptr< ::lestes::std::set< ulint > > spillgen::regs_used_by_groups_get() const
00305 {
00306 return regs_used_by_groups;
00307 }
00308
00309
00310
00311
00312
00313 void spillgen::regs_used_by_groups_set(const ptr< ::lestes::std::set< ulint > > & x)
00314 {
00315 spillgen::regs_used_by_groups = x;
00316 }
00317
00318
00319
00320
00321
00322 ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_pi > > > spillgen::curr_generated_instructions_get() const
00323 {
00324 return curr_generated_instructions;
00325 }
00326
00327
00328
00329
00330
00331 void spillgen::curr_generated_instructions_set(const ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_pi > > > & x)
00332 {
00333 spillgen::curr_generated_instructions = x;
00334 }
00335
00336
00337
00338
00339
00340 ptr< spillgen > spillgen::create(ptr< ::lestes::backend_v2::structs::func_data > a__worker_base__data,
00341 ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::workers::alloc_interval > > > a__spillgen__active_intervals,
00342 ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::workers::alloc_interval > > > a__spillgen__expired_intervals,
00343 ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::workers::alloc_interval > > > a__spillgen__waiting_intervals,
00344 ptr< ::lestes::std::set< ulint > > a__spillgen__free_registers,
00345 ptr< ::lestes::std::set< ulint > > a__spillgen__used_registers,
00346 ptr< ::lestes::std::set< ulint > > a__spillgen__all_registers,
00347 ptr< ::lestes::std::map< ulint, srp< ::lestes::backend_v2::workers::alloc_interval > > > a__spillgen__register_owners,
00348 ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::pi_mem_factory > > > a__spillgen__free_spill_spaces,
00349 ptr< ::lestes::md::registers::move_generator > a__spillgen__move_gen,
00350 bool a__spillgen__registers_freed,
00351 ptr< ::lestes::std::map< srp< ::lestes::backend_v2::intercode::pi_mem_factory >, srp< ::lestes::backend_v2::intercode::ge_pi > > > a__spillgen__spill_space_last_use,
00352 ptr< ::lestes::std::map< ulint, srp< ::lestes::backend_v2::intercode::ge_pi > > > a__spillgen__register_last_use,
00353 ptr< ::lestes::std::map< srp< ::lestes::backend_v2::intercode::ge_operand_reg >, srp< ::lestes::backend_v2::workers::alloc_interval > > > a__spillgen__op2interval,
00354 ptr< ::lestes::std::map< srp< ::lestes::backend_v2::intercode::ge_operand_reg >, srp< spillgen_group > > > a__spillgen__op2group,
00355 ptr< ::lestes::std::list< srp< spillgen_group > > > a__spillgen__groups,
00356 ptr< ::lestes::std::set< ulint > > a__spillgen__regs_used_by_groups,
00357 ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_pi > > > a__spillgen__curr_generated_instructions)
00358 {
00359 return ptr< spillgen > ( new spillgen(a__worker_base__data,
00360 a__spillgen__active_intervals,
00361 a__spillgen__expired_intervals,
00362 a__spillgen__waiting_intervals,
00363 a__spillgen__free_registers,
00364 a__spillgen__used_registers,
00365 a__spillgen__all_registers,
00366 a__spillgen__register_owners,
00367 a__spillgen__free_spill_spaces,
00368 a__spillgen__move_gen,
00369 a__spillgen__registers_freed,
00370 a__spillgen__spill_space_last_use,
00371 a__spillgen__register_last_use,
00372 a__spillgen__op2interval,
00373 a__spillgen__op2group,
00374 a__spillgen__groups,
00375 a__spillgen__regs_used_by_groups,
00376 a__spillgen__curr_generated_instructions) );
00377 }
00378
00379
00380
00381
00382
00383 ptr< spillgen > spillgen::create(ptr< ::lestes::backend_v2::structs::func_data > a__worker_base__data)
00384 {
00385 return ptr< spillgen > ( new spillgen(a__worker_base__data, ::lestes::std::vector< srp< ::lestes::backend_v2::workers::alloc_interval > > ::create(), ::lestes::std::vector< srp< ::lestes::backend_v2::workers::alloc_interval > > ::create(), NULL, ::lestes::std::set< ulint > ::create(), ::lestes::std::set< ulint > ::create(), ::lestes::std::set< ulint > ::create(), ::lestes::std::map< ulint, srp< ::lestes::backend_v2::workers::alloc_interval > > ::create(), ::lestes::std::set< srp< ::lestes::backend_v2::intercode::pi_mem_factory > > ::create(), NULL, false, ::lestes::std::map< srp< ::lestes::backend_v2::intercode::pi_mem_factory >, srp< ::lestes::backend_v2::intercode::ge_pi > > ::create(), ::lestes::std::map< ulint, srp< ::lestes::backend_v2::intercode::ge_pi > > ::create(), ::lestes::std::map< srp< ::lestes::backend_v2::intercode::ge_operand_reg >, srp< ::lestes::backend_v2::workers::alloc_interval > > ::create(), ::lestes::std::map< srp< ::lestes::backend_v2::intercode::ge_operand_reg >, srp< spillgen_group > > ::create(), ::lestes::std::list< srp< spillgen_group > > ::create(), ::lestes::std::set< ulint > ::create(), ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_pi > > ::create()) );
00386 }
00387
00388
00389
00390
00391
00392 spillgen::spillgen (ptr< ::lestes::backend_v2::structs::func_data > a__worker_base__data,
00393 ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::workers::alloc_interval > > > a__spillgen__active_intervals,
00394 ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::workers::alloc_interval > > > a__spillgen__expired_intervals,
00395 ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::workers::alloc_interval > > > a__spillgen__waiting_intervals,
00396 ptr< ::lestes::std::set< ulint > > a__spillgen__free_registers,
00397 ptr< ::lestes::std::set< ulint > > a__spillgen__used_registers,
00398 ptr< ::lestes::std::set< ulint > > a__spillgen__all_registers,
00399 ptr< ::lestes::std::map< ulint, srp< ::lestes::backend_v2::workers::alloc_interval > > > a__spillgen__register_owners,
00400 ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::pi_mem_factory > > > a__spillgen__free_spill_spaces,
00401 ptr< ::lestes::md::registers::move_generator > a__spillgen__move_gen,
00402 bool a__spillgen__registers_freed,
00403 ptr< ::lestes::std::map< srp< ::lestes::backend_v2::intercode::pi_mem_factory >, srp< ::lestes::backend_v2::intercode::ge_pi > > > a__spillgen__spill_space_last_use,
00404 ptr< ::lestes::std::map< ulint, srp< ::lestes::backend_v2::intercode::ge_pi > > > a__spillgen__register_last_use,
00405 ptr< ::lestes::std::map< srp< ::lestes::backend_v2::intercode::ge_operand_reg >, srp< ::lestes::backend_v2::workers::alloc_interval > > > a__spillgen__op2interval,
00406 ptr< ::lestes::std::map< srp< ::lestes::backend_v2::intercode::ge_operand_reg >, srp< spillgen_group > > > a__spillgen__op2group,
00407 ptr< ::lestes::std::list< srp< spillgen_group > > > a__spillgen__groups,
00408 ptr< ::lestes::std::set< ulint > > a__spillgen__regs_used_by_groups,
00409 ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_pi > > > a__spillgen__curr_generated_instructions)
00410 : worker_base(a__worker_base__data), active_intervals(checked(a__spillgen__active_intervals)), expired_intervals(checked(a__spillgen__expired_intervals)), waiting_intervals(a__spillgen__waiting_intervals), free_registers(checked(a__spillgen__free_registers)), used_registers(checked(a__spillgen__used_registers)), all_registers(checked(a__spillgen__all_registers)), register_owners(checked(a__spillgen__register_owners)), free_spill_spaces(checked(a__spillgen__free_spill_spaces)), move_gen(a__spillgen__move_gen), registers_freed(a__spillgen__registers_freed), spill_space_last_use(checked(a__spillgen__spill_space_last_use)), register_last_use(checked(a__spillgen__register_last_use)), op2interval(checked(a__spillgen__op2interval)), op2group(checked(a__spillgen__op2group)), groups(checked(a__spillgen__groups)), regs_used_by_groups(checked(a__spillgen__regs_used_by_groups)), curr_generated_instructions(checked(a__spillgen__curr_generated_instructions))
00411 {}
00412
00413 ptr< object::reflection_list > spillgen::reflection_get() const
00414 {
00415 if (!reflection) {
00416 typedef class_reflection::field_metadata md;
00417 typedef class_reflection::field_metadata_list mdlist;
00418 ptr<mdlist> mdl = mdlist::create();
00419 mdl->push_back( md::create( "active_intervals", "vector< srp< ::lestes::backend_v2::workers::alloc_interval > >" ) );
00420 mdl->push_back( md::create( "expired_intervals", "vector< srp< ::lestes::backend_v2::workers::alloc_interval > >" ) );
00421 mdl->push_back( md::create( "waiting_intervals", "vector< srp< ::lestes::backend_v2::workers::alloc_interval > >" ) );
00422 mdl->push_back( md::create( "free_registers", "set< ulint >" ) );
00423 mdl->push_back( md::create( "used_registers", "set< ulint >" ) );
00424 mdl->push_back( md::create( "all_registers", "set< ulint >" ) );
00425 mdl->push_back( md::create( "register_owners", "map< ulint, srp< ::lestes::backend_v2::workers::alloc_interval > >" ) );
00426 mdl->push_back( md::create( "free_spill_spaces", "set< srp< ::lestes::backend_v2::intercode::pi_mem_factory > >" ) );
00427 mdl->push_back( md::create( "move_gen", "move_generator" ) );
00428 mdl->push_back( md::create( "registers_freed", "bool" ) );
00429 mdl->push_back( md::create( "spill_space_last_use", "map< srp< ::lestes::backend_v2::intercode::pi_mem_factory >, srp< ::lestes::backend_v2::intercode::ge_pi > >" ) );
00430 mdl->push_back( md::create( "register_last_use", "map< ulint, srp< ::lestes::backend_v2::intercode::ge_pi > >" ) );
00431 mdl->push_back( md::create( "op2interval", "map< srp< ::lestes::backend_v2::intercode::ge_operand_reg >, srp< ::lestes::backend_v2::workers::alloc_interval > >" ) );
00432 mdl->push_back( md::create( "op2group", "map< srp< ::lestes::backend_v2::intercode::ge_operand_reg >, srp< spillgen_group > >" ) );
00433 mdl->push_back( md::create( "groups", "list< srp< spillgen_group > >" ) );
00434 mdl->push_back( md::create( "regs_used_by_groups", "set< ulint >" ) );
00435 mdl->push_back( md::create( "curr_generated_instructions", "set< srp< ::lestes::backend_v2::intercode::ge_pi > >" ) );
00436 reflection = reflection_list::create( worker_base::reflection_get() );
00437 reflection->push_back( class_reflection::create( "spillgen", mdl ) );
00438 }
00439 return reflection;
00440 }
00441
00442 ptr< object::field_list_list > spillgen::field_values_get() const
00443 {
00444 ptr < field_list_list > result = worker_base::field_values_get();
00445 result->push_back( value_list::create() );
00446 result->back()->push_back( this->active_intervals );
00447 result->push_back( value_list::create() );
00448 result->back()->push_back( this->expired_intervals );
00449 result->push_back( value_list::create() );
00450 result->back()->push_back( this->waiting_intervals );
00451 result->push_back( value_list::create() );
00452 result->back()->push_back( this->free_registers );
00453 result->push_back( value_list::create() );
00454 result->back()->push_back( this->used_registers );
00455 result->push_back( value_list::create() );
00456 result->back()->push_back( this->all_registers );
00457 result->push_back( value_list::create() );
00458 result->back()->push_back( this->register_owners );
00459 result->push_back( value_list::create() );
00460 result->back()->push_back( this->free_spill_spaces );
00461 result->push_back( value_list::create() );
00462 result->back()->push_back( this->move_gen );
00463 result->push_back( value_list::create() );
00464 result->back()->push_back( objectize< bool > ::create( this->registers_freed ) );
00465 result->push_back( value_list::create() );
00466 result->back()->push_back( this->spill_space_last_use );
00467 result->push_back( value_list::create() );
00468 result->back()->push_back( this->register_last_use );
00469 result->push_back( value_list::create() );
00470 result->back()->push_back( this->op2interval );
00471 result->push_back( value_list::create() );
00472 result->back()->push_back( this->op2group );
00473 result->push_back( value_list::create() );
00474 result->back()->push_back( this->groups );
00475 result->push_back( value_list::create() );
00476 result->back()->push_back( this->regs_used_by_groups );
00477 result->push_back( value_list::create() );
00478 result->back()->push_back( this->curr_generated_instructions );
00479 return result;
00480 }
00481
00482
00483
00484
00485
00486
00487 void spillgen::gc_mark()
00488 {
00489 worker_base::gc_mark();
00490 }
00491
00492
00493
00494
00495
00496
00497
00498
00499
00500 ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_operand_reg > > > spillgen_group::operands_get() const
00501 {
00502 return operands;
00503 }
00504
00505
00506
00507
00508
00509 void spillgen_group::operands_set(const ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_operand_reg > > > & x)
00510 {
00511 spillgen_group::operands = x;
00512 }
00513
00514
00515
00516
00517
00518 ptr< ::lestes::std::set< ulint > > spillgen_group::allowed_registers_get() const
00519 {
00520 return allowed_registers;
00521 }
00522
00523
00524
00525
00526
00527 void spillgen_group::allowed_registers_set(const ptr< ::lestes::std::set< ulint > > & x)
00528 {
00529 spillgen_group::allowed_registers = x;
00530 }
00531
00532
00533
00534
00535
00536 ptr< ::lestes::std::set< ulint > > spillgen_group::avail_regs_for_input_ops_get() const
00537 {
00538 return avail_regs_for_input_ops;
00539 }
00540
00541
00542
00543
00544
00545 void spillgen_group::avail_regs_for_input_ops_set(const ptr< ::lestes::std::set< ulint > > & x)
00546 {
00547 spillgen_group::avail_regs_for_input_ops = x;
00548 }
00549
00550
00551
00552
00553
00554 ptr< ::lestes::std::set< ulint > > spillgen_group::avail_regs_for_output_ops_get() const
00555 {
00556 return avail_regs_for_output_ops;
00557 }
00558
00559
00560
00561
00562
00563 void spillgen_group::avail_regs_for_output_ops_set(const ptr< ::lestes::std::set< ulint > > & x)
00564 {
00565 spillgen_group::avail_regs_for_output_ops = x;
00566 }
00567
00568
00569
00570
00571
00572 ptr< ::lestes::md::registers::tm_register > spillgen_group::reg_get() const
00573 {
00574 return reg;
00575 }
00576
00577
00578
00579
00580
00581 void spillgen_group::reg_set(const ptr< ::lestes::md::registers::tm_register > & x)
00582 {
00583 spillgen_group::reg = x;
00584 }
00585
00586
00587
00588
00589
00590 ptr< spillgen_group > spillgen_group::guarded_group_get() const
00591 {
00592 return guarded_group;
00593 }
00594
00595
00596
00597
00598
00599 void spillgen_group::guarded_group_set(const ptr< spillgen_group > & x)
00600 {
00601 spillgen_group::guarded_group = x;
00602 }
00603
00604
00605
00606
00607
00608 bool spillgen_group::is_input_get() const
00609 {
00610 return is_input;
00611 }
00612
00613
00614
00615
00616
00617 void spillgen_group::is_input_set(bool x)
00618 {
00619 spillgen_group::is_input = x;
00620 }
00621
00622
00623
00624
00625
00626 bool spillgen_group::is_output_get() const
00627 {
00628 return is_output;
00629 }
00630
00631
00632
00633
00634
00635 void spillgen_group::is_output_set(bool x)
00636 {
00637 spillgen_group::is_output = x;
00638 }
00639
00640
00641
00642
00643
00644 ptr< ::lestes::backend_v2::intercode::ge_operand_mem > spillgen_group::backup_space_get() const
00645 {
00646 return backup_space;
00647 }
00648
00649
00650
00651
00652
00653 void spillgen_group::backup_space_set(const ptr< ::lestes::backend_v2::intercode::ge_operand_mem > & x)
00654 {
00655 spillgen_group::backup_space = x;
00656 }
00657
00658
00659
00660
00661
00662 ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::intercode::ge_pi > > > spillgen_group::backup_instructions_get() const
00663 {
00664 return backup_instructions;
00665 }
00666
00667
00668
00669
00670
00671 void spillgen_group::backup_instructions_set(const ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::intercode::ge_pi > > > & x)
00672 {
00673 spillgen_group::backup_instructions = x;
00674 }
00675
00676
00677
00678
00679
00680 ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_pi > > > spillgen_group::load_instructions_get() const
00681 {
00682 return load_instructions;
00683 }
00684
00685
00686
00687
00688
00689 void spillgen_group::load_instructions_set(const ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_pi > > > & x)
00690 {
00691 spillgen_group::load_instructions = x;
00692 }
00693
00694
00695
00696
00697
00698 ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_pi > > > spillgen_group::store_instructions_get() const
00699 {
00700 return store_instructions;
00701 }
00702
00703
00704
00705
00706
00707 void spillgen_group::store_instructions_set(const ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_pi > > > & x)
00708 {
00709 spillgen_group::store_instructions = x;
00710 }
00711
00712
00713
00714
00715
00716 ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::intercode::ge_pi > > > spillgen_group::restore_instructions_get() const
00717 {
00718 return restore_instructions;
00719 }
00720
00721
00722
00723
00724
00725 void spillgen_group::restore_instructions_set(const ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::intercode::ge_pi > > > & x)
00726 {
00727 spillgen_group::restore_instructions = x;
00728 }
00729
00730
00731
00732
00733
00734 ptr< spillgen_group > spillgen_group::create(ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_operand_reg > > > a__spillgen_group__operands,
00735 ptr< ::lestes::std::set< ulint > > a__spillgen_group__allowed_registers,
00736 ptr< ::lestes::std::set< ulint > > a__spillgen_group__avail_regs_for_input_ops,
00737 ptr< ::lestes::std::set< ulint > > a__spillgen_group__avail_regs_for_output_ops,
00738 ptr< ::lestes::md::registers::tm_register > a__spillgen_group__reg,
00739 ptr< spillgen_group > a__spillgen_group__guarded_group,
00740 bool a__spillgen_group__is_input,
00741 bool a__spillgen_group__is_output,
00742 ptr< ::lestes::backend_v2::intercode::ge_operand_mem > a__spillgen_group__backup_space,
00743 ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::intercode::ge_pi > > > a__spillgen_group__backup_instructions,
00744 ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_pi > > > a__spillgen_group__load_instructions,
00745 ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_pi > > > a__spillgen_group__store_instructions,
00746 ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::intercode::ge_pi > > > a__spillgen_group__restore_instructions)
00747 {
00748 return ptr< spillgen_group > ( new spillgen_group(a__spillgen_group__operands,
00749 a__spillgen_group__allowed_registers,
00750 a__spillgen_group__avail_regs_for_input_ops,
00751 a__spillgen_group__avail_regs_for_output_ops,
00752 a__spillgen_group__reg,
00753 a__spillgen_group__guarded_group,
00754 a__spillgen_group__is_input,
00755 a__spillgen_group__is_output,
00756 a__spillgen_group__backup_space,
00757 a__spillgen_group__backup_instructions,
00758 a__spillgen_group__load_instructions,
00759 a__spillgen_group__store_instructions,
00760 a__spillgen_group__restore_instructions) );
00761 }
00762
00763
00764
00765
00766
00767 ptr< spillgen_group > spillgen_group::create()
00768 {
00769 return ptr< spillgen_group > ( new spillgen_group(::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_operand_reg > > ::create(), NULL, NULL, NULL, NULL, NULL, false, false, NULL, NULL, ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_pi > > ::create(), ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_pi > > ::create(), NULL) );
00770 }
00771
00772
00773
00774
00775
00776 spillgen_group::spillgen_group (ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_operand_reg > > > a__spillgen_group__operands,
00777 ptr< ::lestes::std::set< ulint > > a__spillgen_group__allowed_registers,
00778 ptr< ::lestes::std::set< ulint > > a__spillgen_group__avail_regs_for_input_ops,
00779 ptr< ::lestes::std::set< ulint > > a__spillgen_group__avail_regs_for_output_ops,
00780 ptr< ::lestes::md::registers::tm_register > a__spillgen_group__reg,
00781 ptr< spillgen_group > a__spillgen_group__guarded_group,
00782 bool a__spillgen_group__is_input,
00783 bool a__spillgen_group__is_output,
00784 ptr< ::lestes::backend_v2::intercode::ge_operand_mem > a__spillgen_group__backup_space,
00785 ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::intercode::ge_pi > > > a__spillgen_group__backup_instructions,
00786 ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_pi > > > a__spillgen_group__load_instructions,
00787 ptr< ::lestes::std::set< srp< ::lestes::backend_v2::intercode::ge_pi > > > a__spillgen_group__store_instructions,
00788 ptr< ::lestes::std::vector< srp< ::lestes::backend_v2::intercode::ge_pi > > > a__spillgen_group__restore_instructions)
00789 : ::lestes::std::object(), operands(checked(a__spillgen_group__operands)), allowed_registers(a__spillgen_group__allowed_registers), avail_regs_for_input_ops(a__spillgen_group__avail_regs_for_input_ops), avail_regs_for_output_ops(a__spillgen_group__avail_regs_for_output_ops), reg(a__spillgen_group__reg), guarded_group(a__spillgen_group__guarded_group), is_input(a__spillgen_group__is_input), is_output(a__spillgen_group__is_output), backup_space(a__spillgen_group__backup_space), backup_instructions(a__spillgen_group__backup_instructions), load_instructions(checked(a__spillgen_group__load_instructions)), store_instructions(checked(a__spillgen_group__store_instructions)), restore_instructions(a__spillgen_group__restore_instructions)
00790 {}
00791
00792 ptr< object::reflection_list > spillgen_group::reflection_get() const
00793 {
00794 if (!reflection) {
00795 typedef class_reflection::field_metadata md;
00796 typedef class_reflection::field_metadata_list mdlist;
00797 ptr<mdlist> mdl = mdlist::create();
00798 mdl->push_back( md::create( "operands", "set< srp< ::lestes::backend_v2::intercode::ge_operand_reg > >" ) );
00799 mdl->push_back( md::create( "allowed_registers", "set< ulint >" ) );
00800 mdl->push_back( md::create( "avail_regs_for_input_ops", "set< ulint >" ) );
00801 mdl->push_back( md::create( "avail_regs_for_output_ops", "set< ulint >" ) );
00802 mdl->push_back( md::create( "reg", "tm_register" ) );
00803 mdl->push_back( md::create( "guarded_group", "spillgen_group" ) );
00804 mdl->push_back( md::create( "is_input", "bool" ) );
00805 mdl->push_back( md::create( "is_output", "bool" ) );
00806 mdl->push_back( md::create( "backup_space", "ge_operand_mem" ) );
00807 mdl->push_back( md::create( "backup_instructions", "vector< srp< ::lestes::backend_v2::intercode::ge_pi > >" ) );
00808 mdl->push_back( md::create( "load_instructions", "set< srp< ::lestes::backend_v2::intercode::ge_pi > >" ) );
00809 mdl->push_back( md::create( "store_instructions", "set< srp< ::lestes::backend_v2::intercode::ge_pi > >" ) );
00810 mdl->push_back( md::create( "restore_instructions", "vector< srp< ::lestes::backend_v2::intercode::ge_pi > >" ) );
00811 reflection = reflection_list::create( ::lestes::std::object::reflection_get() );
00812 reflection->push_back( class_reflection::create( "spillgen_group", mdl ) );
00813 }
00814 return reflection;
00815 }
00816
00817 ptr< object::field_list_list > spillgen_group::field_values_get() const
00818 {
00819 ptr < field_list_list > result = ::lestes::std::object::field_values_get();
00820 result->push_back( value_list::create() );
00821 result->back()->push_back( this->operands );
00822 result->push_back( value_list::create() );
00823 result->back()->push_back( this->allowed_registers );
00824 result->push_back( value_list::create() );
00825 result->back()->push_back( this->avail_regs_for_input_ops );
00826 result->push_back( value_list::create() );
00827 result->back()->push_back( this->avail_regs_for_output_ops );
00828 result->push_back( value_list::create() );
00829 result->back()->push_back( this->reg );
00830 result->push_back( value_list::create() );
00831 result->back()->push_back( this->guarded_group );
00832 result->push_back( value_list::create() );
00833 result->back()->push_back( objectize< bool > ::create( this->is_input ) );
00834 result->push_back( value_list::create() );
00835 result->back()->push_back( objectize< bool > ::create( this->is_output ) );
00836 result->push_back( value_list::create() );
00837 result->back()->push_back( this->backup_space );
00838 result->push_back( value_list::create() );
00839 result->back()->push_back( this->backup_instructions );
00840 result->push_back( value_list::create() );
00841 result->back()->push_back( this->load_instructions );
00842 result->push_back( value_list::create() );
00843 result->back()->push_back( this->store_instructions );
00844 result->push_back( value_list::create() );
00845 result->back()->push_back( this->restore_instructions );
00846 return result;
00847 }
00848
00849
00850
00851
00852
00853
00854 void spillgen_group::gc_mark()
00855 {
00856 ::lestes::std::object::gc_mark();
00857 }
00858
00859
00860
00861
00862
00863 ptr<object::reflection_list> spillgen::reflection = reflection;
00864 ptr<object::reflection_list> spillgen_group::reflection = reflection;
00865
00866 end_package(workers);
00867 end_package(backend_v2);
00868 end_package(lestes);
00869